论文标题
在降压FPGA BRAMS操作下，多层感知器（MLP）的功率和准确性（MLP）
Power and Accuracy of Multi-Layer Perceptrons (MLPs) under Reduced-voltage FPGA BRAMs Operation
论文作者
论文摘要
在本文中，我们利用了磁场可编程栅极阵列（FPGA）的块RAMS（BRAM）的侵略性电源电压下压力，以提高多层感知器（MLPS）的能效。此外，我们评估并提高了该加速器的弹性。通过对几种代表性FPGA织物的实验，我们观察到，直到最小安全电压水平，即VMIN MLP精度不影响MLP的精度。这个安全区域涉及大型电压防护带。同样，它涉及一个较窄的电压区域，由于电路延迟的增加，故障开始出现在记忆中，但是这些故障被MLP掩盖，因此，其准确性不会受到影响。但是，由于快速增加的高断层率，进一步的低估会导致明显的准确损失。基于这些未成年故障故障的表征，我们提出了缓解断层技术，可以有效地改善此类加速器的弹性行为。我们的评估基于四个FPGA平台。平均而言，我们的能源节省量> 90％，精度损失高达0.1％。
In this paper, we exploit the aggressive supply voltage underscaling technique in Block RAMs (BRAMs) of Field Programmable Gate Arrays (FPGAs) to improve the energy efficiency of Multi-Layer Perceptrons (MLPs). Additionally, we evaluate and improve the resilience of this accelerator. Through experiments on several representative FPGA fabrics, we observe that until a minimum safe voltage level, i.e., Vmin the MLP accuracy is not affected. This safe region involves a large voltage guardband. Also, it involves a narrower voltage region where faults start to appear in memories due to the increased circuit delay, but these faults are masked by MLP, and thus, its accuracy is not affected. However, further undervolting causes significant accuracy loss as a result of the fast-increasing high fault rates. Based on the characterization of these undervolting faults, we propose fault mitigation techniques that can effectively improve the resilience behavior of such accelerator. Our evaluation is based on four FPGA platforms. On average, we achieve >90% energy saving with a negligible accuracy loss of up to 0.1%.
