论文标题
快速极地解码器的硬件实现的操作合并
Operation Merging for Hardware Implementations of Fast Polar Decoders
论文作者
论文摘要
极性代码是一类线性块代码，可证明可以实现通道容量。它们已被选为增强移动宽带（EMBB）方案的控制通道的编码方案，价格为$ 5^{\ text {th}} $ generation nireless Communication Networks（5G），并正在考虑用于额外使用方案。结果，极地代码的快速解码技术至关重要。以前针对的针对连续策略的吞吐量（SC）的吞吐量是极地代码的分解的，是利用特殊最大似然（ML）节点的半平行实现。在这项工作中，我们提出了新的快速简化SC（FAST-SSC）解码器体系结构。与基线FAST-SSC解码器相比，我们的解决方案能够减少内存要求。我们通过更有效的内存利用来实现这一目标，这也使能够在单个时钟周期内执行多个操作。最后，我们提出了新的特殊节点合并技术，以进一步改善吞吐量，并详细介绍新的基于快速SSC的解码器体系结构以支持合并的操作。提议的解码器将操作序列要求降低了$ 39 \％$，这使得可以将代码字解码的时间步骤减少$ 35 \％$。 65 nm TSMC技术的ASIC实施结果表明，与以前的FAST-SSC解码器体系结构相比，提议的解码器的吞吐量提高了高达$ 31 \％$。
Polar codes are a class of linear block codes that provably achieves channel capacity. They have been selected as a coding scheme for the control channel of enhanced mobile broadband (eMBB) scenario for $5^{\text{th}}$ generation wireless communication networks (5G) and are being considered for additional use scenarios. As a result, fast decoding techniques for polar codes are essential. Previous works targeting improved throughput for successive-cancellation (SC) decoding of polar codes are semi-parallel implementations that exploit special maximum-likelihood (ML) nodes. In this work, we present a new fast simplified SC (Fast-SSC) decoder architecture. Compared to a baseline Fast-SSC decoder, our solution is able to reduce the memory requirements. We achieve this through a more efficient memory utilization, which also enables to execute multiple operations in a single clock cycle. Finally, we propose new special node merging techniques that improve the throughput further, and detail a new Fast-SSC-based decoder architecture to support merged operations. The proposed decoder reduces the operation sequence requirement by up to $39\%$, which enables to reduce the number of time steps to decode a codeword by $35\%$. ASIC implementation results with 65 nm TSMC technology show that the proposed decoder has a throughput improvement of up to $31\%$ compared to previous Fast-SSC decoder architectures.
