论文标题
旋转波浪归一化朝所有宏伟的电路
Spin Wave Normalization Towards all Magnonic Circuits
论文作者
论文摘要
自旋波(SW)技术利用用于构建超低功率电路的关键促进因素是能够有效地级联SW基本计算块的能力。 SW多数门构成了该范式的通用门,在相位编码的数据上运行的不是输入输出在SW振幅方面相干,因此,它们的级联需要从SW到电压和返回的信息表示,这绝不是能量有效的。在本文中,提出了一种新型的无转换栅极级联方案,该方案通过方向耦合器来实现SW振幅归一化。在引入了标准化概念之后,我们将其用于实施三个简单电路,并证明其更大的规模潜力(2位输入SW乘数)。所提出的结构通过面向对象的微磁框架(OOMMF)和GPU加速微型磁学(MUMAX3)验证。此外,我们评估了归一化诱导的能量开销,并证明与基于传感器的常规对应物相比,所提出的方法消耗的能量少20%至33%。最后,我们引入了基于归一化的SW 2位输入乘数设计,并将其与功能等效的基于SW传感器和16NM CMOS设计进行比较。我们的评估表明,与常规方法和16NM CMOS相比,所提出的方法分别提供了26%和6.25倍的能量降低,这表明我们的提议具有能源有效,并为SW范式的全面利用开辟了道路,并仅开发了SW电路的发展。
The key enabling factor for Spin Wave (SW) technology utilization for building ultra low power circuits is the ability to energy efficiently cascade SW basic computation blocks. SW Majority gates, which constitute a universal gate set for this paradigm, operating on phase encoded data are not input output coherent in terms of SW amplitude, and as such, their cascading requires information representation conversion from SW to voltage and back, which is by no means energy effective. In this paper, a novel conversion free SW gate cascading scheme is proposed that achieves SW amplitude normalization by means of a directional coupler. After introducing the normalization concept, we utilize it in the implementation of three simple circuits and, to demonstrate its bigger scale potential, of a 2-bit inputs SW multiplier. The proposed structures are validated by means of the Object Oriented Micromagnetic Framework (OOMMF) and GPU-accelerated Micromagnetics (MuMax3). Furthermore, we assess the normalization induced energy overhead and demonstrate that the proposed approach consumes 20% to 33% less energy when compared with the transducers based conventional counterpart. Finally, we introduce a normalization based SW 2-bit inputs multiplier design and compare it with functionally equivalent SW transducer based and 16nm CMOS designs. Our evaluation indicate that the proposed approach provided 26% and 6.25x energy reductions when compared with the conventional approach and 16nm CMOS counterpart, respectively, which demonstrates that our proposal is energy effective and opens the road towards the full utilization of the SW paradigm potential and the development of SW only circuits.