论文标题
RISC微处理器验证
RISC micrprocessor verification
论文作者
论文摘要
当今的微处理器在复杂性和功能上已经显着增长。当今的大多数处理器至少提供三个级别的内存层次结构,大量管道供水,并支持某种形式的缓存相干协议。这些功能非常复杂且精致,并提出了自己的一套独特的验证挑战。验证显然不是一个点工具,而是从初始产品概念开始的过程的一部分,并且在产品上市时就在一定程度上完成。对于在RTL级别验证功能是必要的功能验证。诸如ARM之类的复杂微处理器是高性能,低成本和低功率32位RISC处理器。在我们的纸复合物中,微处理器是ARM Cortex M3,它是为嵌入式应用程序开发的,其中断潜伏期低,门计数低,3级管道,分支预测,拇指和Thumb-2指令集。功能验证用于验证该电路是否填充了实现映射下的每个抽象断言。我们探讨了处理器设计的几个方面,包括缓存,管道深度,Alus和旁路逻辑。该验证与处理器的设计实现同时进行。
Today's microprocessors have grown significantly in complexity and functionality. Most of today's processors provide at least three levels of memory hierarchy, are heavily pipelined, and support some sort of cache coherency protocol. These features are extremely complex and sophisticated, and present their own set of unique verification challenges. Verification is clearly not a point tool, but is part of a process that starts from initial product conception and is to some degrees complete when the product goes to market. Functional verification is necessary to verify the functionality at RTL level. Complex micro-processors like ARM are high performance, low cost and low power 32-bit RISC processors. In our paper complex microprocessor is ARM cortex M3, developed for the embedded applications having low interrupt latency, low gate count, 3- stage pipelining, branch prediction, THUMB and THUMB-2 instruction set. Functional verification is used to verify that the circuit full fills each abstract assertion under the implementation mapping. we explore several aspects of processor design, including caches, pipeline depth, ALUs, and bypass logic.The verification was done concurrently with the design implementation of the processor.