论文标题
逻辑电路的可扩展攻击性混淆
Scalable Attack-Resistant Obfuscation of Logic Circuits
论文作者
论文摘要
硬件IP保护一直是过去几年中最关键的研究领域之一。最近，随着攻击者开发了复杂的技术，对硬件IP的攻击已经发展。因此，已经引入了硬件混淆，作为保护IPS免受盗版攻击的强大工具。但是，最近的许多打破现有混淆方法的尝试已经成功解锁IP并恢复其功能。在本文中，我们提出了Saro，这是一种可扩展的抗攻击性混淆，提供了强大的功能和结构设计转换过程。 Saro将目标电路视为图形，并执行分区算法以产生一组子图形，然后将我们的新颖真实表变换（T3）过程应用于每个分区。我们还提出了$ T3_ {Metric} $，该$是为了量化由混淆过程引起的结构和功能设计转换级别的开发。我们在ISCAS85和EPFL基准上评估Saro，并对我们提出的框架提供全面的安全性和性能分析。
Hardware IP protection has been one of the most critical areas of research in the past years. Recently, attacks on hardware IPs (such as reverse engineering or cloning) have evolved as attackers have developed sophisticated techniques. Therefore, hardware obfuscation has been introduced as a powerful tool to protect IPs against piracy attacks. However, many recent attempts to break existing obfuscation methods have been successful in unlocking the IP and restoring its functionality. In this paper, we propose SARO, a Scalable Attack-Resistant Obfuscation that provides a robust functional and structural design transformation process. SARO treats the target circuit as a graph, and performs a partitioning algorithm to produce a set of sub-graphs, then applies our novel Truth Table Transformation (T3) process to each partition. We also propose the $T3_{metric}$, which is developed to quantify the structural and functional design transformation level caused by the obfuscation process. We evaluate SARO on ISCAS85 and EPFL benchmarks, and provide full security and performance analysis of our proposed framework.
