论文标题

Belle II的Arich on-deTector fpgas的型间构型擦洗

Intermodular Configuration Scrubbing of On-detector FPGAs for the ARICH at Belle II

论文作者

Giordano, R., Lai, Y., Korpar, S., Pestotnik, R., Lozar, A., Santelj, L., Shoji, M., Nishida, S.

论文摘要

高能物理实验中的探测器数字电子产品越来越多地通过基于SRAM的FPGA来实施,因为它们的重新配置,实时处理和多数观数据传输的能力。辐射诱导的单个事件在配置中的启动阻碍了正确的操作,因为它们可能会更改编程的路由路径和逻辑功能。在大多数触发和数据采集系统中,来自几个前端模块的数据集中在一个板上,然后将数据传输到后端电子设备以获取和触发。由于前端模块是相同的,因此它们具有相同的FPGA,这些FPGA用相同的bitstream编程。在这项工作中,我们提出了一种新颖的洗涤器,能够通过大多数在不同模块上投票通过大多数投票来校正辐射诱导的软座。我们展示了该系统在Kek实验室Superkekb(日本Tsukuba)的Belle2实验的Air胶圈成像Cherenkov(Arich)亚探测器的读出的电子设备中的应用。我们在集中器板上的VirTex-5 LX50T FPGA中讨论了该系统的架构及其在有关前端模块的virtex-5 LX50T FPGA中的实现,以纠正最多六个Spartan-6 LX45 FPGA的配置。我们讨论了Jozef Stefan Institute(Slovenia Ljubljana)Triga反应堆的故障注射和中子辐照测试的结果,我们将解决方案的性能与Xilinx软误差缓解控制器进行了比较。

On-detector digital electronics in High-Energy Physics experiments is increasingly being implemented by means of SRAM-based FPGA, due to their capabilities of reconfiguration, real-time processing and multi-gigabit data transfer. Radiation-induced single event upsets in the configuration hinder the correct operation, since they may alter the programmed routing paths and logic functions. In most trigger and data acquisition systems, data from several front-end modules are concentrated into a single board, which then transmits data to back-end electronics for acquisition and triggering. Since the front-end modules are identical, they host identical FPGAs, which are programmed with the same bitstream. In this work, we present a novel scrubber capable of correcting radiation-induced soft-errors in the configuration of SRAM-based FPGAs by majority voting across different modules. We show an application of this system to the read-out electronics of the Aerogel Ring Imaging CHerenkov (ARICH) subdetector of the Belle2 experiment at SuperKEKB of the KEK laboratory (Tsukuba, Japan). We discuss the architecture of the system and its implementation in a Virtex-5 LX50T FPGA, in the concentrator board, for correcting the configuration of up to six Spartan-6 LX45 FPGAs, on pertaining front-end modules. We discuss results from fault-injection and neutron irradiation tests at the TRIGA reactor of the Jozef Stefan Institute (Ljubljana, Slovenia) and we compare the performance of our solution to the Xilinx Soft Error Mitigation controller.

扫码加入交流群

加入微信交流群

微信交流群二维码

扫码加入学术交流群,获取更多资源