论文标题
与体系结构相关分析的栅极级侧通道泄漏评估
Gate-Level Side-Channel Leakage Assessment with Architecture Correlation Analysis
论文作者
论文摘要
尽管传统上从制造的芯片中评估了侧通道泄漏，但在芯片的设计阶段这样做是更及时且具有成本效益的。我们提出了一种方法，可以根据设计对芯片侧向通道泄漏的贡献进行排名。该方法依赖于逻辑合成，逻辑模拟，门级功率估计和门泄漏评估来计算排名。排名度量可以通过将栅极级活动与泄漏模型相关联，或通过评估响应级活动来响应不同的测试矢量组来定义为特定测试。我们的结果表明，设计中只有少数大门贡献了大多数侧道泄漏。我们为多种设计展示了此属性，包括五阶段管道的RISC处理器中的硬件AES协处理器和一个加密硬件/软件接口。
While side-channel leakage is traditionally evaluated from a fabricated chip, it is more time-efficient and cost-effective to do so during the design phase of the chip. We present a methodology to rank the gates of a design according to their contribution to the side-channel leakage of the chip. The methodology relies on logic synthesis, logic simulation, gate-level power estimation, and gate leakage assessment to compute a ranking. The ranking metric can be defined as a specific test by correlating gate-level activity with a leakage model, or else as a non-specific test by evaluating gate-level activity in response to distinct test vector groups. Our results show that only a minority of the gates in a design contribute most of the side-channel leakage. We demonstrate this property for several designs, including a hardware AES coprocessor and a cryptographic hardware/software interface in a five-stage pipelined RISC processor.
