论文标题
Emunoc：FPGA上快速，灵活网络原型的混合模拟
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs
论文作者
论文摘要
从多核CPU到Edge-ai加速器，最近广泛使用了芯片网络（NOCS）。与缓慢的模拟相比，FPGA上的仿真有望加速其RTL建模。但是，现实的测试刺激在硬件中为各种应用程序生成具有挑战性。换句话说，需要快速和灵活的设计框架。最有前途的解决方案是混合仿真，其中设计的某些部分在软件中模拟，而其他部分则在硬件中模仿。本文提出了一个称为Emunoc的新型混合模拟框架。我们介绍了一种时钟同步方法和仅软件数据包生成，该方法将模拟速度提高了36.3倍至79.3倍，而不是最新的框架，同时保留了用于刺激模拟的纯软件接口的灵活性。我们还提高了面积效率，以在单个FPGA上使用169个路由器建模到NOC，而以前的框架仅实现了64个路由器。
Networks-on-Chips (NoCs) recently became widely used, from multi-core CPUs to edge-AI accelerators. Emulation on FPGAs promises to accelerate their RTL modeling compared to slow simulations. However, realistic test stimuli are challenging to generate in hardware for diverse applications. In other words, both a fast and flexible design framework is required. The most promising solution is hybrid emulation, in which parts of the design are simulated in software, and the other parts are emulated in hardware. This paper proposes a novel hybrid emulation framework called EmuNoC. We introduce a clock-synchronization method and software-only packet generation that improves the emulation speed by 36.3x to 79.3x over state-of-the-art frameworks while retaining the flexibility of a pure-software interface for stimuli simulation. We also increased the area efficiency to model up to an NoC with 169 routers on a single FPGA, while previous frameworks only achieved 64 routers.
