论文标题

GAN MOS电容器的研究和表征:平面与沟渠地形

Study and characterization of GaN MOS capacitors: planar versus trench topographies

论文作者

Mukherjee, K., De Santi, C., You, S., Geens, K., Borga, M., Decoutere, S., Bakeroot, B., Diehle, P., Altmann, F., Meneghesso, G., Zanoni, E., Meneghini, M.

论文摘要

开发高质量的GAN/介电界面是制造GAN垂直功率晶体管的基本步骤。在本文中,我们定量研究了平面蚀刻处理和沟槽形成对基于GAN的MOS(金属氧化物半导体)堆栈性能的影响。结果表明(i)蚀刻gan表面的毯子不会降解沉积介电层的稳健性; (ii)与平面结构相比,在提高可重复性的同时,添加沟槽蚀刻剂会导致分解性能的降低。 (iii)对于沟渠结构,10年寿命的电压仍高于20 V,表明良好的稳健性。 (iv)要审查在金属二电动堆栈上的捕获性能,进行了有或没有压力和光辅助的前向反向电容 - 电压测量。总体而言,没有先前的蚀刻步骤的生长平面电容器显示出最低的捕获,而沟槽电容器具有较高的界面捕获,并且散装捕获与毯子蚀刻的电容器相当。 (v)GAN/介电界面的纳米结构的特征是高分辨率扫描透射电子显微镜(HR-STEM)。毯子蚀刻后观察到2-3个单层在gan表面的粗糙度增加,这与界面陷阱的较高密度相关。本文介绍的结果给出了有关蚀刻和沟槽加工如何影响沟槽gan-mosfets的诱捕和稳健性的基本见解,并为优化设备性能提供了指导。

Developing high quality GaN/dielectric interfaces is a fundamental step for manufacturing GaN vertical power transistors. In this paper, we quantitatively investigate the effect of planar etching treatment and trench formation on the performance of GaN-based MOS (metal oxide semiconductor) stacks. The results demonstrate that (i) blanket etching the GaN surface does not degrade the robustness of the deposited dielectric layer; (ii) the addition of the trench etch, while improving reproducibility, results in a decrease of breakdown performance compared to the planar structures. (iii) for the trench structures, the voltage for a 10 years lifetime is still above 20 V, indicating a good robustness. (iv) To review the trapping performance across the metal-dielectric-GaN stack, forward-reverse capacitance-voltage measurements with and without stress and photo-assistance are performed. Overall, as-grown planar capacitors devoid of prior etching steps show lowest trapping, while trench capacitors have higher interface trapping, and bulk trapping comparable to the blanket etched capacitors. (v) The nanostructure of the GaN/dielectric interface was characterized by high resolution scanning transmission electron microscopy (HR-STEM). An increased roughness of 2-3 monolayers at the GaN surface was observed after blanket etching, which was correlated to the higher density of interface traps. The results presented in this paper give fundamental insight on how the etch and trench processing affects the trapping and robustness of trench-gate GaN-MOSFETs, and provide guidance for the optimization of device performance.

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