论文标题
与混合原型制作的多锁域MPSOC的快速设计空间探索
Rapid design space exploration of multi-clock domain MPSoCs with hybrid prototyping
论文作者
论文摘要
本文介绍了使用混合原型来对具有多个时钟域的MPSOC设计进行早期功率绩效分析的新技术。混合原型制作的基本思想是通过在核心单个物理实例上创建软件中的仿真内核来模拟设计的设计。但是，到目前为止，混合原型限于以同一时钟频率运行的均匀多粒子。此外，尚未证明混合原型用于有效的设计空间探索。我们的工作着重于增强混合原型的功能，以便将其应用于现实的多锁MPSOC设计以及对MPSOC设计的早期功率绩效评估。我们使用JPEG，MP3和数据包处理等工业强度应用的实验证明了混合原型的高精度，并且超过了两个数量级的改进，而不是软件仿真速度。我们还证明，使用常规FPGA原型制作，使用混合原型探索超过150个设计选项可以在几分钟内使用高可靠性来完成。
This paper presents novel techniques of using hybrid prototyping for early power-performance analysis of MPSoC designs with multiple clock domains. The fundamental idea of hybrid prototyping is to simulate a design with multiple cores by creating an emulation kernel in software on top of a single physical instance of the core. However, so far hybrid prototyping has been limited to homogeneous multicores running at the same clock frequency. Moreover, hybrid prototyping has not yet been demonstrated for efficient design space exploration. Our work focuses on enhancing the capabilities of hybrid prototyping, such that it can be applied to realistic multi-clock MPSoC designs as well to perform early power-performance evaluation of MPSoC designs. Our experiments using industrial strength applications such as JPEG, MP3 and Packet Processing, demonstrate the high accuracy of our hybrid prototypes, and over two orders of magnitude improvement over software simulation speed. We also demonstrate that exploring over 150 design options using hybrid prototyping can be done with high reliability in the order of minutes compared to multiple days using conventional FPGA prototyping.
