论文标题
使用硬件驱动的DNN的低误差近似乘数设计
Low Error-Rate Approximate Multiplier Design for DNNs with Hardware-Driven Co-Optimization
论文作者
论文摘要
在本文中，提出了两个大约3*3个乘数，ASAP-7NM过程库的合成结果证明，它们可以将面积降低31.38％和36.17％，而与精确乘数相比，功耗分别可以减少36.73％和35.66％。它们可以使用2*2乘法器聚合，以根据DNN权重的分布产生具有较低误差率的8*8乘数。我们提出了一种由硬件驱动的软件合作方法，以通过重新培训提高DNN精度。基于提出的两个大约3位乘数，为DNN设计了三个具有低误差率的近似8位乘数。与确切的8位未签名乘数相比，我们的设计比公共数据集上的其他近似乘数可以实现重大优势。
In this paper, two approximate 3*3 multipliers are proposed and the synthesis results of the ASAP-7nm process library justify that they can reduce the area by 31.38% and 36.17%, and the power consumption by 36.73% and 35.66% compared with the exact multiplier, respectively. They can be aggregated with a 2*2 multiplier to produce an 8*8 multiplier with low error rate based on the distribution of DNN weights. We propose a hardware-driven software co-optimization method to improve the DNN accuracy by retraining. Based on the proposed two approximate 3-bit multipliers, three approximate 8-bit multipliers with low error-rate are designed for DNNs. Compared with the exact 8-bit unsigned multiplier, our design can achieve a significant advantage over other approximate multipliers on the public dataset.
