论文标题
在高光度Atlas Tilecal Link子板上进行的辐射研究
Radiation studies performed on the High Luminosity ATLAS TileCal link Daughterboard
论文作者
论文摘要
HL-LHC的Atlas Tile量热仪的新电子设备通过子板将探测器和探测器电子设备接口。子板的定位位置为具有商业SFPS+，CERN GBTX ASIC，Proasic FPGA和Kintex Ultrascale FPGAS的定位。该设计通过双重冗余方案，三模冗余，Xilinx软错误减轻IP，用于链路数据传输的CRC/FEC和SEL保护电路来最大程度地减少单个故障点，并通过双冗余方案，三模冗余，Xilinx软误差IP，CRC/FEC来最大程度地减轻辐射损伤。我们提供了TID，NIEL和查看资格测试的最新摘要，以及儿子板修订6 Design的绩效研究。
The new electronics of the ATLAS Tile Calorimeter for the HL-LHC interfaces the on-detector and off-detector electronics by means of a Daughterboard. The Daughterboard is positioned on-detector featuring commercial SFPs+, CERN GBTx ASICs, ProASIC FPGAs and Kintex Ultrascale FPGAs. The design minimizes single points of failure and mitigates radiation damage by means of a double redundant scheme, Triple Mode Redundancy, Xilinx Soft Error Mitigation IP, CRC/FEC for link data transfer, and SEL protection circuitry. We present an updated summary of the TID, NIEL and SEE qualification tests, and performance studies of the Daughterboard revision 6 design.
